This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-096280, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor package with a semiconductor chip disposed therein and containing, for example, a vertical type MOS transistor, and a manufacturing method thereof.
2. Description of the Related Art
FIG. 17A is a plan view diagram showing a conventional semiconductor package with a power semiconductor chip disposed therein and containing a vertical type MOS transistor. FIGS. 17B and 17C are sectional view diagrams of the semiconductor package shown in FIG. 17A, in the longitudinal direction and a direction perpendicular thereto, respectively.
As shown in FIGS. 17A to 17C, a power semiconductor chip 102 is mounted on a device-mounting portion (bed portion) 110 of a lead frame 101 through a solder layer 103. The lead frame 101 is made of a material, such as Cu, a Cu alloy, Fe-42Ni alloy. The lead frame 101 includes the bed portion 110, a first lead 111, a second lead 112, and a third lead 113 integrally connected to the bed portion 110. The chip 102 includes a MOS transistor formed of a source region, a base region, a drain region, a gate electrode, and so forth.
A metal electrode 107a of, e.g., Al, and a metal electrode 107b of, e.g., Au or Al are disposed on the top side of the chip 102. The metal electrode 107a is electrically connected to the source region and the base region through a source electrode (including a source lead-out electrode). The metal electrode 107b is electrically connected to the gate electrode (including a gate lead-out electrode).
The metal electrodes 107a and 107b of the chip 102 are electrically connected to the first and second leads 111 and 112 through bonding wires 116 and 114 of, e.g., an Au wire. The chip 102, the bed portion 110, the proximal portions of the first, second, and third leads 111 to 113, and the bonding wires 116 and 114 are resin-sealed by a resin sealing body 105 of, e.g., epoxy resin.
The conventional semiconductor package shown in FIGS. 17A to 17C entails the following problems. A plurality of Au wires are used for a chip containing a power semiconductor device, such as a vertical type MOS transistor, to reduce the wiring resistance due to the Au wires. In this case, the number of indexes of assembling steps increases with an increase in the number of electrode pads and thus with an increase in the number of connecting Au wires. Furthermore, it is difficult to further reduce the wiring resistance by design due to the wire length.
On the other hand, a power semiconductor chip requires a good heat-discharge property to be ensured. In light of the heat-discharge property, it is preferable to increase the thickness of the bed portion of a lead frame on which the chip is mounted. In this case, however, the thickness of the lead frame itself needs to be increased, thereby making the entire semiconductor package bulky. Where the lead frame is formed to have a larger thickness only at the bed portion, the product cost of the lead frame remarkably increases. Accordingly, such a lead frame could not be used for a package product in practice.
U.S. Pat. No. 6,040,626 discloses a structure in which a first lead is directly bonded to a semiconductor chip of a vertical type MOS transistor by a conductive bonding material to reduce the wiring resistance. In this structure, however, the heat-discharge property of the semiconductor chip is hardly improved, but the lead projecting from a resin sealing body prevents the package from being compact.
Accordingly, there are demands for a semiconductor package, the entire size of which does not have to be increased, even where it has a semiconductor chip with a larger current rating, such as a power semiconductor chip containing a vertical type MOS transistor.
According to a first aspect of the present invention, there is provided a semiconductor package, comprising:
a semiconductor chip including first and second electrodes disposed on a top side, and a third electrode disposed on a bottom side;
a heat spreader bonded to the third electrode;
first and second conductive leads electrically connected to the first and second electrodes through first and second conductive bonding members, respectively, the first and second leads respectively including foot portions, which laterally extend at lower ends of the first and second leads and are juxtaposed on a first side of the heat spreader; and
an insulating sealing body arranged to embed and seal therein the semiconductor chip, the heat spreader, and portions of the first and second leads, which extend from the first and second bonding members to at least part of the foot portions, the heat spreader and the foot portions of the first and second leads having bottom faces, which are exposed on a bottom of the sealing body, and are disposed on substantially the same plane.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor package comprising:
bonding a heat spreader to a third electrode of a semiconductor chip, which includes first and second electrodes disposed on a top side, and the third electrode disposed on a bottom side
electrically connecting first and second conductive leads to the first and second electrodes by first and second conductive bonding members, respectively, the first and second leads respectively including foot portions, which laterally extend at lower ends of the first and second leads and are juxtaposed on a first side of the heat spreader; and
forming an insulating sealing body to embed and seal therein the semiconductor chip, the heat spreader, and portions of the first and second leads, which extend from the first and second bonding members to at least part of the foot portions, the heat spreader and the foot portions of the first and second leads having bottom faces, which are exposed on a bottom of the sealing body, and are disposed on substantially the same plane.
According to a third aspect of the present invention, there is provided a semiconductor package, comprising:
a semiconductor chip including first and second electrodes disposed on a top side, and a third electrode disposed on a bottom side;
a conductive heat spreader bonded to the third electrode, the heat spreader being electrically connected to the third electrode through a third conductive bonding member, and functioning as a third lead;
first and second conductive leads electrically connected to the first and second electrodes through first and second conductive bonding members, respectively, wherein each of the first and second leads is formed of a conductive strip, and the heat spreader has a thickness t1 and the conductive strip has a thickness t2 to satisfy a thickness ratio condition of 1 less than t1/t2xe2x89xa63, wherein each of the first and second leads comprises a proximal portion facing the top side of the semiconductor chip, a leg portion bending from the proximal portion and extending along a flank of the semiconductor chip and the heat spreader, and a foot portion bending from the leg portion and extending away from the heat spreader, and wherein the foot portions of the first and second leads are juxtaposed on a first side of the heat spreader; and
an insulating sealing body arranged to embed and seal therein the semiconductor chip, the heat spreader, and all the proximal portions and the leg portions of the first and second leads, and at least part of the foot portions of the first and second leads, wherein the sealing body consists essentially of a material selected from the group consisting of thermosetting resins including epoxy resin, and wherein the heat spreader and the foot portions of the first and second leads have bottom faces, which are exposed on a bottom of the sealing body, and are disposed on substantially the same plane.